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rev. 1.0 10/07 copyright ? 2007 by silicon laboratories si4730/31-a10 silicon laboratories confidential. information contained herein is covered under non-disclosure agreement (nda). si4730/31-a10 b roadcast am/fm r adio r eceiver features applications description the si4730/31 is the first digital cmos am /fm radio receiver ic that integrates the complete tuner function fr om antenna input to audio output. functional block diagram worldwide fm band support (76?108 mhz) worldwide am band support (520?1710 khz) excellent real-world performance freq synthesizer with integrated vco advanced am/fm seek tuning automatic frequency control (afc) automatic gain control (agc) integrated ldo regulator digital fm stereo decoder programmable de-emphasis adaptive noise suppression am/fm digital tuning no manual alignment necessary programmable reference clock volume control programmable soft mute control rds/rbds processor (si4731 only) 2-wire and 3-wire control interface 2.7 to 5.5 v supply voltage firmware upgradeable wide range of ferrite loop sticks and air loop antennas supported 3 x 3 x 0.55 mm 20-pin qfn package pb-free/rohs compliant table and portable radios stereos mini/micro systems cd/dvd players portable media players boom boxes cellular handsets modules clock radios mini hifi entertainment systems car radios adc adc si473x dsp dac dac fmi fm ant vio 1.5-3.6v sclk sdio control interface sen rst rout lout ldo vdd gnd 2.7 - 5.5 v rds (si4731) am ant rfgnd ami lna lna low-if agc agc afc rclk patents pending notes: 1. to ensure proper operation and receiver performance, follow the guidelines in ?an384: si4730/31 am/fm receiver layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 2. place si4730/31 as close as possible to antenna jack and keep the fmi and ami traces as short as possible. ordering information: see page 25. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio nc lout rout gnd rst nc ami rclk sdio vdd fmi rfgnd gpo3 nc gpo1 nc sclk sen si4730/31-gm (top view)
si4730/31-a10 2 rev. 1.0
si4730/31-a10 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3. fm receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4. am receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.5. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6. de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4.7. stereo dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8. soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9. rds/rbds processor (si4731 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11. seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.12. reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4.14. gpo outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.15. firmware upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.16. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.17. programming wi th commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. commands and propertie s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. pin descriptions: si4730/ 31-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1. si4730/31 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. package outline: si4730/ 31 qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10. pcb land pattern: si4730/31 qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
si4730/31-a10 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage v dd 2.7 ? 5.5 v interface supply voltage v io 1.5 ? 3.6 v power supply powe r-up rise time v ddrise 10 ? ? s interface power supply power-up rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 c note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at vdd = 3.3 v and 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 5.8 v interface supply voltage v io ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (vio + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si4730/31 devices are high-performanc e rf integrated circuits with certain pins having an esd rating of < 2 kv hbm. handling and assembly of these devices sh ould only be done at esd-protected workstations. 3. for input pins sclk, sen, sdio, rst, rclk, gpo1, gpo2, and gpo3. 4. at rf input pins, fmi and ami.
si4730/31-a10 rev. 1.0 5 table 3. dc characteristics (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit fm mode supply current i fm ?19.222ma supply current 1 i fm low snr level ? 19.8 23 ma rds supply current i fm ?19.923ma am mode supply current i am analog output mode ? 16.8 20.5 ma supplies and interface interface supply current i io ?400820a powerdown current 2 i dd ?1020 a interface powerdown current 2 i io sclk, rclk inactive ? 1 10 a high level input voltage 3 v ih 0.7 x vio ? ? v low level input voltage 3 v il ??0.3xviov high level input current 3 i ih v in = vio = 3.6 v ?10 ? 10 a low level input current 3 i il v in =0v, v io =3.6v ?10 ? 10 a high level output voltage 4 v oh i out = 500 a 0.8 x vio ? ? v low level output voltage 4 v ol i out = ?500 a ? ? 0.2 x vio v notes: 1. lna is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 2. specifications are guaran teed by characterization. 3. for input pins sclk, sen, sdio, rst, and rclk. 4. for output pins sdio, gpo1, gpo2, and gpo3.
si4730/31-a10 6 rev. 1.0 figure 1. reset timing parameters for busmode select table 4. reset timing characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol min typ max unit rst pulse width and gpo1, gpo2/int setup to r st 4 t srst 100 ? ? s gpo1, gpo2/int hold from r st t hrst 30 ? ? ns important notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure t hat sclk is high during the rising edge of rst , and stays high until after the 1st start condition. 3. when selecting 3-wire or spi modes, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 4. if gpo1 and gpo2 are actively driven by the user, then minimum t srst is only 30 ns. if gpo1 or gpo2 is hi-z, then minimum t srst is 100 s, to provide time for on-chip 1 m devices (active while rst is low) to pull gpo1 high and gpo2 low. 70% 30% gpo1 70% 30% gpo2/ int 70% 30% t srst rst t hrst
si4730/31-a10 rev. 1.0 7 table 5. 2-wire control interface characteristics 1,2,3 (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio setup (start) t su:sta 0.6 ? ? s sclk input to sdio hold (start) t hd:sta 0.6 ? ? s sdio input to sclk setup t su:dat 100 ? ? ns sdio input to sclk hold 4,5 t hd:dat 0?900ns sclk input to sdio setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out 20 + 0.1 x c b ?250ns sdio input, sclk rise/fall time t f:in t r:in 20 + 0.1 x c b ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when vio = 0 v, sclk and sdio are low impedance. 2. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst , and stays high until after the 1st start condition. 4. the si4730/31 delays sdio by a minimum of 300 ns from t he vih threshold of sclk to comply with the 0 ns t hd:dat specification. 5. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated so long as all other timing parameters are met.
si4730/31-a10 8 rev. 1.0 figure 2. 2-wire control interface read and write timing parameters figure 3. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0
si4730/31-a10 rev. 1.0 9 figure 4. 3-wire control interface write timing parameters figure 5. 3-wire control interface read timing parameters table 6. 3-wire control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk ??2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 20 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen 10 ? ? ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r , t f ? ? 10 ns note: when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio a7 a0 70% 30% t s t s t hsdio t hsen a6-a5, r/w, a4-a1 address in data in d15 d14-d1 d0 t high t low t r t f ? cycle bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio t cdv t cdz address in data out a7 a0 a6-a5, r/w, a4-a1 d15 d14-d1 d0 t s t s t hsen
si4730/31-a10 10 rev. 1.0 figure 6. spi control interface write timing parameters figure 7. spi control interface read timing parameters table 7. spi control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 15 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen 5??ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r , t f ? ? 10 ns note: when selecting spi mode, the user must ensure that a rising edge of sclk d oes not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio c7 c0 70% 30% t s c6 ?c1 control byte in 8 data bytes in d7 d6 ?d1 d0 t s t hsdio t high t low t hsen t f t r bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio control byte in c7 c0 c6 ?c1 t s t hsen t s t cdz t cdv 16 data bytes out (sdio or gpo1) d7 d6 ?d1 d0
si4730/31-a10 rev. 1.0 11 table 8. fm receiver characteristics 1,2 (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz sensitivity with headphone network 3,4,5 (s+n)/n = 26 db ? 2.2 3.5 v emf sensitivity with 50 network 3,4,5,7 (s+n)/n = 26 db ? 1.1 ? v emf rds sensitivity 7 f=2khz, rds bler < 5% ?15?v emf lna input resistance 6,7 345k lna input capacitance 6,7 456pf input ip3 7,8 100 105 ? dbv emf am suppression 3,4,6,7 m=0.3 40 50 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel selectivity 400 khz 60 70 ? db spurious response rejection 7 in-band 35 ? ? db audio output voltage 3,4,6 72 80 90 mv rms audio output l/r imbalance 3,6,9 ?? 1 db audio band limits 3,6,7 1.5 db 30 ? 15k hz audio stereo separation 6,9 25 ? ? db audio mono s/n 3,4,5,6 56 63 ? db audio stereo s/n 5 ?58?db audio thd 3,6,9 ?0.10.5% de-emphasis time constant 7 fm_deemphasis = 2 70 75 80 s fm_deemphasis = 1 45 50 54 s audio common mode voltage 10 0.7 0.8 0.9 v audio output load resistance 7,10 r l single-ended 10 ? ? k audio output load capacitance 7,10 c l single-ended ? ? 50 pf notes: 1. additional testing information is available in application note an234. volume = maximum for all tests. tested at rf = 100 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an384: si4730/31 am/fm receiver layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 3. f mod = 1 khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. v emf =1 mv. 7. guaranteed by characterization. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2 x f 1 ? f 2 . agc is disabled. refer to "6. pin descriptions: si4730/31-gm" on page 24. 9. f = 75 khz. 10. at lout and rout pins.
si4730/31-a10 12 rev. 1.0 seek/tune time 7 ? ? 80 ms/chan- nel powerup time 7 from powerdown ? ? 110 ms rssi offset input levels of 8 and 60 dbv emf ?3 ? 3db table 9. am receiver characteristics 1 (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, ta = ?20 to 85 c) parameter symbol test condition min typ max unit input frequency f rf 520 ? 1710 khz sensitivity 2,3 (s+n)/n = 26 db ? 38 ? v emf large signal voltage handling 4 thd < 8% ? 300 ? mv rms power supply rejection ratio v dd =100 mv rms , 100 hz ? 40 ? db audio output voltage 2,5 54 60 67 mv rms audio s/n 2,3,5 48 56 ? db audio thd 2,3,5 ? 0.1 0.5 % antenna inductance 4 180 ? 600 h powerup time from powerdown ? ? 110 ms notes: 1. to ensure proper operation and receiver performance, follo w the guidelines in ?an384: si4730/31 am/fm receiver layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 2. fmod = 1 khz, 30% modulation, a-weighted, 2 khz channel filter. 3. f rf = 1000 khz, ' f = 10 khz. 4. guaranteed by characterization. 5. v in = 5 mvrms. table 8. fm receiver characteristics 1,2 (continued) (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit notes: 1. additional testing information is available in application note an234. volume = maximum for all tests. tested at rf = 100 mhz. 2. to ensure proper operation and receiver performance, follo w the guidelines in ?an384: si4730/31 am/fm receiver layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 3. f mod = 1 khz, 75 s de-emphasis, mono = enabled, and l = r unless noted otherwise. 4. ' f = 22.5 khz. 5. b af = 300 hz to 15 khz, a-weighted. 6. v emf =1 mv. 7. guaranteed by characterization. 8. |f 2 ? f 1 | > 2 mhz, f 0 =2 x f 1 ? f 2 . agc is disabled. refer to "6. pin descriptions: si4730/31-gm" on page 24. 9. ' f = 75 khz. 10. at lout and rout pins.
si4730/31-a10 rev. 1.0 13 table 10. reference clock and crystal characteristics (v dd = 2.7 to 5.5 v, vio = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit reference clock rclk supported frequencie 1 31.130 32.768 40,000 khz rclk frequency tolerance 2 ?100 ? 100 ppm refclk_prescale 1 ? 4095 refclk 31.130 32.768 34.406 khz crystal oscillator crystal oscillator frequency ? 32.768 ? khz crystal frequency tolerance 2 ?100 ? 100 ppm board capacitance ? ? 3.5 pf notes: 1. the si4730/31 divides the rclk input by refclk_prescale to obtain refclk. there are some rclk frequencies between 31.130 khz and 40 mhz that are not supported. see an385, table 6 for more details. 2. a frequency tolerance of 50 ppm is required for fm seek/tune using 50 khz channel spacing.
si4730/31-a10 14 rev. 1.0 2. typical application schematic notes: 1. place c1 close to v dd pin. 2. all grounds connect directly to gnd plane on pcb. 3. pins 1 and 20 are no connects, leave floating. 4. to ensure proper operation and receiver performance, follo w the guidelines in ?an384: si4730/31 am/fm receiver layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 5. pin 2 connects to the fm antenna interface, and pin 4 connects to the am antenna interface. 6. rfgnd should be locally isolated from gnd. 7. place si4730/31 as close as possible to antenna jack and keep the fmi and ami traces as short as possible. 20 19 18 17 16 u1 si4730/31-gm nc fmi rfgnd ami rst nc lout rout gnd vdd nc gpo1 gpo2 gpo3 nc sen sclk sdio rclk vio sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 lout rout vbattery 2.7 to 5.5 v gpo1 gpo2/int gpo3 vio 1.5 to 3.6 v fmip c2 c3 x1 rclk gpo3 optional: for crystal oscillator option c5 l1 am antenna optional: am air loop antenna rfgnd ami c5 t1 l2
si4730/31-a10 rev. 1.0 15 3. bill of materials component(s) value/description supplier c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c5 coupling capacitor, 0.47 f, 20%, z5u/x7r murata l1 ferrite loop stick, 180 ? 600 h various u1 si4730/31 am/fm radio tuner silicon laboratories optional components t1 transformer, 1?5 turns ratio various l2 air loop antenna, 10?20 h various c2, c3 crystal load capacitors, 22 pf, 5%, cog (optional: for crystal oscillator option) venkel x1 32.768 khz crystal (optional: fo r crystal oscillator option) epson
si4730/31-a10 16 rev. 1.0 4. functional description 4.1. overview figure 8. functional block diagram the si4730/31 is the industry's first fully integrated, 100% cmos am/fm radio receiver ic. offering unmatched integration and pcb space savings, the si4730/31 requires only two external components and less than 15 mm 2 of board area, excluding the antenna inputs. the si4730/31 am/fm radio provides the space savings and low power consumption necessary for portable devices while deliver ing the high performance and design simplicity desired for all am/fm solutions. leveraging silicon laborator ies' proven and patented si4700/01 fm tuner's digital low intermediate frequency (low-if) receiver architecture, the si4730/31 delivers superior rf performance and interference rejection in both am and fm bands. the high integration and complete system production test simplifies design-in, increases system quality, and improves manufacturability. the si4730/31 is a feature-rich solution including advanced seek algorithms, soft mute, auto-calibrated digital tuning, and fm stereo processing. in addition, the si4730/31 provides a programmable reference clock. the device supports i 2 c-compatible 2-wire control interface, spi, and a si4700/01 backwards-compatible 3-wire control interface. the si4730/31 utilizes digita l processing to achieve high fidelity, optimal performance, and design flexibility. the chip provides excellent pilo t rejection, selectivity, and unmatched audio performance, and offers both the manufacturer and the end-user extensive programmability and flexibility in listening experience. the si4731 incorporates a digital processor for the european radio data system (rds) and the north american radio broadcast data system (rbds) including all required symbol decoding, block synchronization, error detection, and error correction functions. using this feature, the si4731 enables broadcast data such as stat ion identification and song name to be displayed to the user. 4.2. operating modes the si4730/31 operates in either an fm receive or an am receive mode. in fm mode, radio signals are received on fmi (pin 2) and processed by the fm front- end circuitry. in am mode, radio signals are received on ami (pin 4) and processed by the am front-end circuitry. in addition to the receiver mode, there is a clocking mode to choose to clock the si4730/31 from a reference clock or crystal. the receiver mode and the clocking mode are set by the power_up command listed in table 12. si473x command summary. adc adc si473x dsp dac dac fmi fm ant vio 1.5-3.6v sclk sdio control interface sen rst rout lout ldo vdd gnd 2.7 - 5.5 v rds (si4731) am ant rfgnd ami lna lna low-if agc agc afc rclk
si4730/31-a10 rev. 1.0 17 4.3. fm receiver the si4730/31 fm receiver is based on the proven si4700/01 fm tuner. the receiver uses a digital low-if architecture allowing the elimination of external components and factory adjustments. the si4730/31 integrates a low noise amplifier (lna) supporting the worldwide fm broadcast band (76 to 108 mhz). an automatic gain control (agc) circuit controls the gain of the lna to optimize sensitivity and rejection of strong interferers. for testing purposes, the agc can be disabled. refer to section "5. commands and properties" on page 21 for additional programming and configuration information. an image-reject mixer downconverts the rf signal to low-if. the quadrature mixer output is amp lified, filtered, and digitized with high resolution analog-to-digital converters (adcs). this advanced architecture allows the si4730/31 to perform channel selection, fm demodulation, and stereo audio processing to achieve superior performance compared to traditional analog architectures. 4.4. am receiver the highly integrated si4730/31 supports worldwide am band reception from 520 to 1710 khz using a digital low- if architecture with a minimum number of external components and no manual alignment required. this digital low-if architecture allows for high-precision filtering offering excelle nt selectivity and noise suppression. the dsp also provides 9 or 10 khz channel selection, am demodulation, soft mute, and additional features such as adjustable channel bandwidth settings. similar to the fm receiver, the integrated lna and agc op timize sensitivity and rejection of strong interfer ers allowing be tter reception of weak stations. the si4730/31 provides highly accurate digital am tuning without factory adjustments. to offer maximum flexibility, the receiver supp orts a wide range of ferrite loop sticks from 180?600 h. an air loop antenna is supported by using a transformer to increase the effective inductance from the air loop. using a 1:5 turn ratio inductor the inductance is increased by 25x easily supporting all typical am air loop antennas which generally vary between 10 and 20 h. 4.5. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx standard was developed in 1961, and is used worldwide. today's mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds/rbds data as shown in figure 9 below. figure 9. mpx signal spectrum 4.5.1. stereo decoder the si4730/31's integr ated stereo decoder automatically decodes the mpx signal using dsp techniques. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l?r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l?r) signal. output left and right channels are obtained by adding and subtracting the (l+r) and (l?r) signals respectively. the si4731 uses frequency information from the 19 khz stereo pilot to recover the 57 khz rds/rbds signal. 4.5.2. stereo-mono blending adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. stereo/mono status can be monitored with the fm_rsq_status command. mono operation can be forced with the fm_blend_mono_threshold property. 4.6. de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. the si4730/31 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the de- emphasis time constant is programmable to 50 or 75 s and is set by the fm_deemphasis property. 4.7. stereo dac high-fidelity stereo digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted. volume is adjusted digitally with the rx_volume property. 05 7 53 38 231915 frequency (khz) modulation level stereo audio left - right rds/ rbds mono audio left + right stereo pilot
si4730/31-a10 18 rev. 1.0 4.8. soft mute the soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. the softmute atte nuation level is adjustable using the fm_soft_mute_max_attenuation and am_soft_mute_max_attenuation properties. 4.9. rds/rbds processor (si4731 only) the si4731 implements an rds/rbds* processor for symbol decoding, block synchronization, error detection, and error correction. the si4731 device is user configurable and provides an optional interrupt when rds is synchronized, loses synchronization, and/or the user configurable rds fifo threshold has been met. the si4731 reports rds decoder synchronization status, and detailed bit errors in the information word for each rds block with the fm_rds_status command. the range of reportable block errors is 0, 1?2, 3?5, or 6+. more than six errors indicates that the corresponding block information word contains six or more non-correctable errors, or that the block checkword contains errors. *note: rds/rbds is referred to only as rds throughout the remainder of this document. 4.10. tuning the frequency synt hesizer uses silic on laboratories? proven technology, including a completely integrated vco. the frequency synthesizer generates the quadrature local os cillator signal used to downconvert the rf input to a low intermediate frequency. the vco frequency is locked to the reference clock and adjusted with an automatic frequency control (afc) servo loop during reception. the tuning frequency can be directly programmed using the fm_tune_freq and am_tune_freq commands. the si4730/31 supports channel spacing of 50, 100, or 200 khz in fm mode and 9 or 10 khz in am mode. 4.11. seek seek tuning will search up or down for a valid channel. valid channels are found when the receive signal strength indicator (rssi) and the signal-to-noise ratio (snr) values exceed the set threshold. using the snr qualifier rather than sole ly relying on the more traditional rssi qualifier can reduce false stops and increase the number of valid stations detected. seek is initiated using the fm_seek_start and am_seek_start commands. the rssi and snr threshold settings are adjustable using properties (see table 13). two seek options are available. the device will either wrap or stop at the band limits. if the seek operation is unable to find a channel, the device will indicate failure and return to the channel selected before the seek operation began. 4.12. reference clock the si4730/31 reference clock is programmable, supporting rclk frequencies in table 10. refer to table 3, ?dc characteristics,? on page 5 for switching voltage levels and table 8, ?fm receiver characteristics? on page 11 for frequency tolerance information. an onboard crystal oscillator is available to generate the 32.768 khz reference when an external crystal and load capacitors are provided. refe r to "2. typical application schematic" on page 14. this mode is enabled using the power_up command, see table 12, ?si473x command summary,? on page 21. the si4730/31 performance may be affected by data activity on the sdio bus when using the integrated internal oscillator. sdio activity results from polling the tuner for status or commun icating with other devices that share the sdio bus. if there is sdio bus activity while the si4730/31 is performing the seek/tune function, the crystal oscilla tor may experience jitter, which may result in mistunes , false stops, and/or lower snr. for best seek/tun e results, silicon laboratories recommends that all sdio data traffic be suspended during si4730/31 seek and tune operations. this is achieved by keeping the bus quiet for all other devices on the bus, and delaying tu ner polling until the tune or seek operation is complete. the stc (seek/tune complete) interrupt should be used instea d of polling to determine when a seek/tune operation is complete. 4.13. control interface a serial port slave interface is provided, which allows an external controller to send commands to the si4730/31, and receive responses from the device. the serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or spi mode. the si4730/31 selects the bus mode by sampling the state of the gpo1 and gpo2 pins on the rising edge of rst . the gpo1 pin includes an internal pull-up resist or which is connected while rst is low, and the gpo2 pin includes an internal pull- down resistor which is connected while rst is low. therefore, it is only necessary for the user to actively drive pins which differ from these states. see table 11.
si4730/31-a10 rev. 1.0 19 after the rising edge of rst , the pins gpo1 and gpo2 are used as general purpose output (o) pins as described in section ?4.14. gpo outputs?. in any bus mode, commands may only be sent after vio and vdd supplies are applied. in any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (cts bit is high). 4.13.1. 2-wire cont rol interface mode when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst , and stays high until after the first start condition. also, a start condition must not occur within 300 ns before the rising edge of rst . 2-wire bus mode uses only the sclk and sdio pins for signaling. a transaction begins with the start condition, which occurs when sdio falls while sclk is high. next, the user drives an 8-bit control word serially on sdio, which is captur ed by the device on rising edges of sclk. the control word consists of a seven bit device address, followed by a read/write bit (read = 1, write = 0). the si4730/31 acknowledges the control word by driving sdio low on the next falling edge of sclk. although the si4730/31 will respond to only a single device address, this address can be changed with the sen pin (note that the sen pin is not used for signaling in 2-wire mode). when sen = 0, the seven-bit device address is 0010001b. when sen = 1, the address is 1100011b. for write operations, the user then sends an eight bit data byte on sdio, which is captured by the device on rising edges of sclk. the si4730/31 acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. the user may write up to 8 data bytes in a single 2-wire transaction. the first byte is a command, and the next seven bytes are arguments. for read operations, after the si4730/31 has acknowledged the control byte , it will drive an eight bit data byte on sdio, changing the state of sdio on the falling edge of sclk. the us er acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. if a data byte is not acknowledged, the transact ion will end. the user may read up to 16 data bytes in a single 2-wire transaction. these bytes contain the response data from the si4730/31. a 2-wire transaction ends with the stop condition, which occurs when sdio rises while sclk is high. for details on timing specific ations and diagrams, refer to table 5, ?2-wire control interface characteristics? on page 7, figure 2, ?2-wire control interface read and write timing parameters,? on page 8 and figure 3, ?2- wire control interface read and write timing diagram,? on page 8. 4.13.2. 3-wire cont rol interface mode when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 3-wire bus mode uses the sclk, sdio and sen _ pins. a transaction begins when the user drives sen low. next, the user drives a 9- bit control word on sdio, which is captured by the device on rising edges of sclk. the control word consists of a three-bit device address (a7:a5 = 101b), a read/write bit (read = 1, write = 0), and a five-bit register address (a4:a0). for write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of sclk. for read operations, the cont rol word is followed by a delay of one-half sclk cycle for bus turn-around. next, the si4730/31 will drive the 16-bit read data word serially on sdio, changing the state of sdio on each rising edge of sclk. a transaction ends when the user sets sen high, then pulses sclk high and low one final time. sclk may either stop or continue to toggle while sen is high. in 3-wire mode, commands are sent by first writing each argument to register(s) 0xa1?0xa3, then writing the command word to register 0xa0. a response is retrieved by reading registers 0xa8?0xaf. for details on timing specific ations and diagrams, refer to table 6, ?3-wire control in terface characteristics,? on page 9, figure 4, ?3-wire control interface write timing parameters,? on page 9, and figure 5, ?3-wire control interface read timing pa rameters,? on page 9. 4.13.3. spi control interface mode when selecting spi mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . spi bus mode uses the sclk, sdio and sen pins for read/write operations. the system controller can choose to receive read data from the device on either table 11. bus mode select on rising edge of rst bus mode gpo1 gpo2 2-wire 1 0 spi 1 1 (must drive) 3-wire 0 (must drive) 0
si4730/31-a10 20 rev. 1.0 sdio or gpo1. a transaction begins when the system controller drives sen = 0. the system controller then pulses sclk eight times, while driving an 8-bit control byte serially on sdio. the device captures the data on rising edges of sclk. the control byte must have one of five values: 0x48 = write a command (controller drives 8 additional bytes on sdio). 0x80 = read a response (device drives one additional byte on sdio). 0xc0 = read a response (device drives 16 additional bytes on sdio). 0xa0 = read a response (device drives one additional byte on gpo1). 0xe0 = read a response device drives 16 additional bytes on gpo1). for write operations, the s ystem controller must drive exactly 8 data bytes (a command and seven arguments) on sdio after the control byte. the data is captured by the device on the rising edge of sclk. for read operations, the controller must read exactly one byte (status) after the control byte or exactly 16 data bytes (status and resp1?resp15) after the control byte. the device changes the state of sdio (or gpo1, if specified) on the falling edge of sclk. data must be captured by the system controller on the rising edge of sclk. keep sen low until all bytes have transferred. a transaction may be aborted at any time by setting sen high and toggling sclk high and then low. commands will be ignored by the devic e if the transaction is aborted. for details on timing specifications and diagrams, refer to figure 6 and figure 7 on page 10. 4.14. gpo outputs gpo2 can be configured to provide interrupts for seek and tune complete, receive signal quality, and rds. gpo1 and gpo3 are not available on si4730-a10 and si4731-a10. 4.15. firmware upgrades the si4730/31 contains on-chip program ram to accommodate minor changes to the firmware. this allows silicon labs to pr ovide future firmware updates to optimize the characterist ics of new radio designs and those already deployed in the field. 4.16. reset, power up, and powerdown setting the rst pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. setting the rst pin high will bring the device out of reset. a powerdown mode is available to reduce power consumption when the part is idle. putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 4.17. programming with commands to ease development time and offer maximum customization, the si4730/3 1 provides a simple yet powerful software interface to program the receiver. the device is programmed using commands, arguments, properties and responses. to perform an action, the user writes a command byte and associated arguments causing the chip to execute the given command. commands control an action such as power up the device, shut down the device, or tune to a station. arguments are specific to a given command and are used to modify the command. a complete list of commands is available in table 12, ?si473x command summary,? on page 21. properties are a special command argument used to modify the default chip operation and are generally configured immediately after power-up. examples of properties are de-emphasis level, rssi seek threshold, and soft mute attenuation threshold. a complete list of properties is available in table 13, ?si473x property summary,? on page 21. responses provide the user information and are echoed after a command and associated arguments are issued. all commands provide a one-byte status update indicating interrupt and clear-to-send status information. for a detailed description of the commands and properties for the si4730/31, see ?an385: si4730/31 am/fm receiver programming guide.?
si4730/31-a10 rev. 1.0 21 5. commands and properties table 12. si473x command summary cmd name description 0x01 power_up power up device and mode selection. modes include am or fm receive and reference clock or crystal support. 0x10 get_rev returns revision information on the device. 0x11 power_down power down device. 0x12 set_property sets the value of a property. 0x13 get_property retrieves a property?s value. 0x14 get_int_status read interrupt status bits. 0x15 patch_args reserved command us ed for firmware file downloads. 0x16 patch_data reserved command us ed for firmware file downloads. 0x20 fm_tune_freq selects the fm tuning frequency. 0x21 fm_seek_start begins sear ching for a va lid frequency 0x22 fm_tune_status queries the status of previous fm_tune_freq or fm_seek_start command. 0x23 fm_rsq_status queries the status of the received signal quality (rsq) of the current channel. 0x24 fm_rds_status returns rds information for current channel and reads an entry from the rds fifo (si4731 only). 0x40 am_tune_freq tunes to a given am frequency. 0x41 am_seek_start begins searching for a valid frequency. 0x42 am_tune_status queries the status of the already issued am_tune_freq or am_seek_start command. 0x43 am_rsq_status queries the status of the received signal quality (rsq) for the current channel. table 13. si473x property summary prop name description default 0x0001 gpo_ien enables interrupt sources. 0x0000 0x0201 refclk_freq sets frequency of reference clock in hz. the range is 31130 to 34406 hz, or 0 to disable the afc. default is 32768 hz. 0x8000 0x0202 refclk_prescale sets the prescaler value for rclk input. 0x0001 0x1100 fm_deemphasis sets deemphasis time constant. default is 75 us. 0x0002 0x1105 fm_blend_stereo_ threshold sets rssi threshold for stereo blend (full stereo above thresh- old, blend below threshold). to force stereo set this to 0. to force mono set this to 127. default value is 49 dbuv. 0x0031 0x1106 fm_blend_mono_ threshold sets rssi threshold for mono blend (full mono below thresh- old, blend above threshold). to force stereo set this to 0. to force mono set this to 127. default value is 30 dbuv. 0x001e 0x1108 fm_max_tune_ error sets the maximum freq error allowed before setting the afc rail (afcrl) indicator. default value is 30 khz. 0x001e 0x1200 fm_rsq_int_ source configures interrupt re lated to received signa l quality metrics. 0x0000
si4730/31-a10 22 rev. 1.0 0x1201 fm_rsq_snr_hi_ threshold sets high threshold for snr interrupt. 0x007f 0x1202 fm_rsq_snr_lo_ threshold sets low threshold for snr interrupt. 0x0000 0x1203 fm_rsq_rssi_hi_ threshold sets high threshold for rssi interrupt. 0x007f 0x1204 fm_rsq_rssi_lo_ threshold sets low threshold for rssi interrupt. 0x0000 0x1207 fm_rsq_blend_ threshold sets the blend threshold for blend interrupt when boundary is crossed. 0x0081 0x1300 fm_soft_mute_rate sets the attack and decay rates when entering and leaving soft mute. 0x0040 0x1302 fm_soft_mute_ max_attenuation sets maximum attenuation during soft mute (db). set to 0 to dis- able soft mute. default is 16 db. 0x0010 0x1303 fm_soft_mute_ snr_threshold sets snr threshold to engage soft mute. default is 4 db. 0x0004 0x1400 fm_seek_band_ bottom sets the bottom of the fm band for seek. default is 8750. 0x222e 0x1401 fm_seek_band_top sets the top of the fm band for seek. defa ult is 10790. 0x2a26 0x1402 fm_seek_freq_ spacing selects frequency spacing for fm seek. 0x000a 0x1403 fm_seek_tune_ snr_threshold sets the snr threshold for a valid fm seek/tune. default value is 3 db. 0x0003 0x1404 fm_seek_tune_ rssi_treshold sets the rssi threshold for a valid fm seek/tune. default value is 20 dbuv. 0x0014 0x1500 rds_int_source configures rds interrupt behavior. 0x0000 0x1501 rds_int_fifo_count sets the minimum number of rds groups stored in the receive rds fifo required befo re rds recv is set. 0x0000 0x1502 rds_config configures rds setting. 0x0000 0x3100 am_deemphasis sets deemphasis time constant. can be set to 50 us. deempha- sis is disabled by default. 0x0000 0x3102 am_channel_filter selects the bandwidth of the channel filter for am reception. the choices are 6, 4, 3, or 2 (khz). the default bandwidth is 2 khz. 0x0003 0x3200 am_rsq_interrupts configures interrupt re lated to received signal quality metrics. all interrupts are disabled by default. 0x0000 0x3201 am_rsq_snr_high_ threshold sets high threshold for snr interrupt. the default is 0 db. 0x0000 0x3202 am_rsq_snr_low_ threshold sets low threshold for snr interrupt. the default is 0 db. 0x0000 0x3203 am_rsq_rssi_high_ threshold sets high threshold for rssi interrupt. the default is 0 db. 0x0000 0x3204 am_rsq_rssi_low_ threshold sets low threshold for rssi interrupt. the default is 0 db. 0x0000 0x3300 am_soft_mute_rate sets the rate of attack when ent ering or leaving soft mute. the default is 278 db/s. 0x0040 0x3301 am_soft_mute_slope se ts the am soft mute slope. the bigger the number, the higher the max attenuation level. default value is a slope of 2. 0x0002 table 13. si473x property summary (continued) prop name description default
si4730/31-a10 rev. 1.0 23 0x3302 am_soft_mute_max_ attenuation sets maximum attenuation during soft mute (db). set to 0 to dis- able soft mute. default is 16 db. 0x0010 0x3303 am_soft_mute_snr_ threshold sets snr threshold to engage soft mute. default is 10 db. 0x000a 0x3400 am_seek_band_ bottom sets the bottom of the am band for seek. default is 520. 0x0208 0x3401 am_seek_band_top sets the top of the am band for seek. firmware 1.0 incorrectly defaults to 1721 khz instead of 1710. 0x06ae 0x3402 am_seek_freq_ spacing selects frequency spacing for am seek. default is 10 khz spac- ing. 0x000a 0x3403 am_seek_snr_ threshold sets the snr threshold for a valid am seek/tune. if the value is zero then snr threshold is not considered when doing a seek. default value is 5 db. 0x0005 0x3404 am_seek_rssi_ threshold sets the rssi threshold for a valid am seek/tune. if the value is zero then rssi threshold is not considered when doing a seek. default value is 25 dbuv. 0x0019 0x4000 rx_volume sets the output volume. 0x003f 0x4001 rx_hard_mute mutes the audio output. l and r audio outputs may be muted independently in fm mode. 0x0000 table 13. si473x property summary (continued) prop name description default
si4730/31-a10 24 rev. 1.0 6. pin descriptions: si4730/31-gm pin number(s) name description 1, 20 nc no connect. leave floating. 2 fmi fm rf inputs. fmi should be connected to the antenna trace. 3 rfgnd rf ground. connect to ground plane on pcb. 4 ami am rf input. ami should be connected to the am antenna. 5r s t device reset (active low) input. 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external reference oscillator input. 10 vio i/o supply voltage. 11 v dd supply voltage. may be connected directly to battery. 12, gnd pad gnd ground. connect to ground plane on pcb. 13 rout right audio line output. 14 lout left audio line output. 15, 16 nc no connect. leave floating. 17 gpo3 general purpose output. 18 gpo2/int general purpose output or interrupt pin. 19 gpo1 general purpose output. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio nc lout rout gnd rst nc ami rclk sdio vdd fmi rfgnd gpo3 nc gpo1 nc sclk sen
si4730/31-a10 rev. 1.0 25 7. ordering guide part number* description package type operating temperature si4730-a10-gm am/fm broadcast radio receiver qfn pb-free ?20 to 85 c si4731-a10-gm am/fm broadcast ra dio receiver with rds/rbds qfn pb-free ?20 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si4730/31-a10 26 rev. 1.0 8. package markings (top marks) 8.1. si4730/31 top mark 8.2. top mark explanation mark method: yag laser line 1 marking: part number 30 = si4730, 31 = si4731 firmware revision 10 = firmware revision 1.0 line 2 marking: die revision a = revision a die ttt = internal code internal tracking code. line 3 marking: circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier y = year ww = workweek assigned by the assembly house. corresponds to the last sig- nificant digit of the year and workweek of the mold date. 3010 attt yww 3110 attt yww
si4730/31-a10 rev. 1.0 27 9. package outlin e: si4730/31 qfn figure 10 illustrates the package details for the si4730/31. table 1 4 lists the values for the dimensio ns shown in the illustration. figure 10. 20-pin quad flat no-lead (qfn) table 14. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.200.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si4730/31-a10 28 rev. 1.0 10. pcb land pattern: si4730/31 qfn figure 11 illustrates the pcb land pattern details for the si4730/31-gm. table 1 5 lists the values for the dimensions shown in the illustration. figure 11. pcb land pattern
si4730/31-a10 rev. 1.0 29 table 15. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m- 1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si4730/31-a10 30 rev. 1.0 11. additional reference resources si4730/31 revision a errata an231: si4700/01 headphon e and antenna interface an383: si47xx 3 mm x 3 mm qfn universal layout guide an384: si473x am/fm receiver layout guide an385: si473x am/fm receiver programming guide an386: si473x ferrite loop stick antenna interface an388: si473x am/fm tuner eval uation board test procedure an389: si473x evb quick-start guide si47xx customer support site: http://www.mysilabs.com this site contains all application notes, evaluation b oard schematics and layouts, and evaluation software. nda is required for access. to request access, register at http://www.mysilabs.com and send user?s first and last name, company, nda reference numb er, and mysilabs user name to fminfo@sila bs.com. silicon labs recommends an all lowe r case user name.
si4730/31-a10 rev. 1.0 31 d ocument c hange l ist revision 0.3 to revision 0.5 updated block diagram on page 1 and figure 8 on page 16. removed optional digital audio output and gpo functionality. these feat ures will be supported in future firmware revisions. updated table 3, ?dc characteristics,? on page 5. added spi control interface timing diagrams, figure 6 and figure 7. updated table 8, ?fm receiver characteristics 1,2 ,? on page 11. updated table 9, ?am receiver characteristics 1 ,? on page 12. adjusted crystal frequency tolerance from +/? 200 ppm to +/? 100 ppm. updated values for c5 and l2 in "3. bill of materials" on page 15. updated ?4. functional description? to include appropriate commands and properties. updated table 12, ?si473x command summary,? on page 21. updated table 13, ?si473x property summary,? on page 21. updated "7. ordering guide" on page 25. updated "11. additional reference resources" on page 30. added instructions on gaining access to the secure customer website on p.29. revision 0.5 to revision 0.7 updated am seek tune time. updated rclk and refclk details. updated spi description. updated default values in table 13, ?si473x property summary,? on page 21. added "8. package markings (top marks)" on page 26. added digital audio output information. updated table 4, ?reset timing characteristics 1,2,3 ,? on page 6. updated "4.9. rds/rbds processor (si4731 only)" on page 18. updated "6. pin descriptions: si4730/31-gm" on page 24. revision 0.7 to revision 1.0 updated data sheet to be specific to si4730/31-a10. removed digital output information. updated table 3, ?dc characteristics,? on page 5. updated table 8, ?fm receiver characteristics 1,2 ,? on page 11. updated table 9, ?am rece iver characteristics 1 ,? on page 12.
si4730/31-a10 32 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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